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? semiconductor components industries, llc, 2006 january, 2006 ? rev. 1 1 publication order number: NB7L11M/d NB7L11M 2.5v/3.3v differential 1:2 clock/data fanout buffer/ translator with cml outputs and internal termination description the NB7L11M is a differential 1 ? to ? 2 clock/data distribution chip with internal source termination and cml output structure, optimized for low skew and minimal jitter. the device is functionally equivalent to the ep11, lvep11, or sg11 devices. device produces two identical output copies of clock or data op erating up to 8 ghz or 12 gb/s, respectively. as such, NB7L11M is ideal for sonet, gige, fiber channel, backplane and other clock/data distribution applications. inputs incorporate internal 50 termination resistors and accept lvpecl, cml, lvcsmos, lvttl, or lvds (see table 6). differential 16 ma cml output provides matching internal 50 terminations, and 400 mv output swings when externally terminated, 50 to v cc (see figure 14). the device is offered in a low profile 3x3 mm 16 ? pin qfn package. application notes, models, and support documentation are available at www.onsemi.com. features ? maximum input clock frequency up to 8 ghz typical ? maximum input data rate up to 12 gb/s typical ? < 0.5 ps of rms clock jitter ? < 10 ps of data dependent jitter ? 30 ps typical rise and fall times ? 110 ps typical propagation delay ? 3 ps typical within device skew ? operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? cml output level (400 mv peak ? to ? peak output) differential output only ? 50 internal input and output termination resistors ? functionally compatible with existing 2.5 v/3.3 v lvel, lvep, ep and sg devices ? pb ? free packages are available* figure 1. logic diagram q0 q0 q1 q1 v tclk clk clk v tclk 50 50 *for additional marking information, refer to application note and8002/d. marking diagram* a = assembly location l = wafer lot y = year w = work week = pb ? free package qfn ? 16 mn suffix case 485g http://onsemi.com 16 nb7l 11m alyw 1 see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information (note: microdot may be in either location) *for additional information on our pb ? free strategy and soldering details, please download the on semicon- ductor soldering and mounting t echniques reference manual, solderrm/d.
NB7L11M http://onsemi.com 2 v cc q1 q1 v cc v cc q0 q0 v cc v ee v ee v ee v ee v tclk clk clk v tclk 5678 16 15 14 13 12 11 10 9 1 2 3 4 NB7L11M exposed pad (ep) figure 2. qfn ? 16 pinout (top view) table 1. pin description pin name i/o description 1 v tclk ? internal 50 termination pin for clk 2 clk lvpecl, cml, lvcmos, lvttl, lvds inverted differential clock/data input. (note 1) 3 clk lvpecl, cml, lvcmos, lvttl, lvds noninverted differential clock/data input. (note 1) 4 v tclk ? internal 50 termination pin for clk 5,8,13,16 v cc ? positive supply voltage. all v cc pins must be externally connected to a power supply to guarantee proper operation. 6 q1 cml output inverted clk output 1 with internal 50 source termination resistor. (note 2) 7 q1 cml output noninverted clk output 1 with internal 50 source termination resistor. (note 2) 9,10,11,12 v ee ? negative supply voltage. all v ee pins must be externally connected to a power supply to guarantee proper operation. 14 q0 cml output inverted clk output 0 with internal 50 source termination resistor. (note 2) 15 q0 cml output noninverted clk output 0 with internal 50 source termination resistor. (note 2) ? ep ? exposed pad. the thermally exposed pad on package bottom (see case drawing) must be attached to a heatsinking conduit. it is recommended to connect the ep to the lower potential (v ee ). 1. in the dif ferential configuration when the input termination pins (v tclk , v tclk ) are connected to a common termination voltage or left open, and if no signal is applied on clk and clk then the device will be susceptible to self ? oscillation. 2. cml outputs require 50 receiver termination resistor to v cc for proper operation.
NB7L11M http://onsemi.com 3 table 2. attributes characteristics value esd protection human body model machine model charged device model > 1500 v > 50 v > 500 v moisture sensitivity (note 3) pb pkg pb ? free pkg qfn ? 16 level 1 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 285 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 3.6 v v i input voltage v ee = 0 v v ee v i v cc 3.6 v v inpp differential input voltage |clk ? clk | v cc ? v ee 2.8 v v cc ? v ee < 2.8 v 2.8 |v cc ? v ee | v i in input current through r t (50 resistor) static surge 45 80 ma ma i out output current continuous surge 25 50 ma ma t a operating temperature range qfn ? 16 ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) 0 lfpm 500 lfpm qfn ? 16 qfn ? 16 42 36 c/w c/w jc thermal resistance (junction ? to ? case) 2s2p (note 4) qfn ? 16 3 to 4 c/w t sol wave solder pb pb ? free 265 265 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power).
NB7L11M http://onsemi.com 4 table 4. dc characteristics, clock inputs, cml outputs ( v cc = 2.375 v to 3.465 v, v ee = 0 v, t a = ? 40 c to +85 c) (note 5) symbol characteristic min typ max unit i cc power supply current (input and outputs open) 85 105 ma v oh output high voltage (note 6) v cc ? 60 v cc ? 20 v cc mv v ol output low voltage (note 6) v cc ? 530 v cc ? 420 v cc ? 360 mv differential input driven single ? ended (see figures 10 & 12) (note 8) v th input threshold reference voltage range (note 7) 1125 v cc ? 75 mv v ih single ? ended input high voltage (note 8) v th + 75 v cc mv v il single ? ended input low voltage (note 8) v ee v th ? 75 mv differential inputs driven differentially (see figures 11 & 13) (note 8) v ihclk differential input high voltage 1200 v cc mv v ilclk differential input low voltage v ee v cc ? 75 mv v cmr input common mode range (differential configuration) 1163 v cc ? 38 mv v id differential input voltage (v ihclk ? v ilclk ) 75 2500 mv i ih input high current clk / clk (v tclk /v tclk open) 0 25 100 a i il input low current clk / clk (v tclk /v tclk open) ? 10 0 10 a r tin internal input termination resistor 45 50 55 r tout internal output termination resistor 45 50 55 r te m p coef internal i/o termination resistor temperature coefficient 6.38 m / c note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . 6. cml outputs require 50 receiver termination resistors to v cc for proper operation. 7. v th is applied to the complementary input when operating in single ? ended mode. 8. v cmr min varies 1:1 with v ee , v cmr max varies 1:1 with v cc .
NB7L11M http://onsemi.com 5 table 5. ac characteristics (v cc = 2.375 v to 3.465 v, v ee = 0 v; note 9) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max v outpp output voltage amplitude (@v inppmin ) f in 6 ghz (see figure 3) f in 8 ghz 280 140 400 300 280 140 400 300 280 140 400 300 mv f data maximum operating data rate 10 12 10 12 10 12 gb/s t plh , t phl propagation delay to output differential 70 110 150 70 110 150 70 110 150 ps t skew duty cycle skew (note 10) within ? device skew device ? to ? device skew (note 11) 2.0 3.0 20 5.0 15 50 2.0 3.0 20 5.0 15 50 2.0 3.0 20 5.0 15 50 ps t jitter rms random clock jitter (note 12) f in = 6 ghz f in =8 ghz peak/peak data dependent jitter f in = 2.488 gb/s (note 13) f data =5 gb/s f data =10 gb/s 0.2 0.2 2.0 3.0 5.0 0.5 0.5 5.0 8.0 10 0.2 0.2 2.0 3.0 5.0 0.5 0.5 5.0 8.0 10 0.2 0.2 2.0 3.0 5.0 0.5 0.5 5.0 8.0 10 ps v inpp input voltage swing/sensitivity (differential configuration) (note 14) 75 400 2500 75 400 2500 75 400 2500 mv t r t f output rise/fall times @ 1 ghz q, q (20% ? 80%) 30 60 30 60 30 60 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. measured by forcing v inpp (typ) from a 50% duty cycle clock source. all loading with an external r l = 50 to v cc . input edge rates 40 ps (20% ? 80%). 10. duty cycle skew is measured between differential outputs using the deviations of the sum of tpw ? and tpw+ @1 ghz. 11. device to device skew is measured between outputs under identical transition @ 1 ghz. 12. additive rms jitter with 50% duty cycle clock signal at 8 ghz & 10 ghz. 13. additive peak ? to ? peak data dependent jitter with input nrz data at prbs 2 ^23 ? 1. 14. v inpp (max) cannot exceed v cc ? v ee . input voltage swing is a single ? ended measurement operating in differential mode. figure 3. output voltage amplitude (v outpp ) versus input clock frequency (f in ) at ambient temperature (typical) (v inpp = 400 mv) input frequency (ghz) output voltage amplitude (mv) 500 400 300 200 100 0 12 11 10 9 8 7 6 5 4 3 2 1 0 v cc = 3.3 v v cc = 2.5 v
NB7L11M http://onsemi.com 6 figure 4. typical output waveform at 2.488 gb/s with prbs 2 ^23 ? 1 (v inpp = 75 mv) figure 5. typical output waveform at 5 gb/s with prbs 2 ^23 ? 1 (v inpp = 75 mv) figure 6. typical output waveform at 10.7 gb/s with prbs 2 ^23 ? 1 (v inpp = 75 mv) figure 7. typical output waveform at 12 gb/s with prbs 2 ^23 ? 1 (v inpp = 75 mv) time (80.4 ps/div) time (40 ps/div) time (18.6 ps/div) time (18.2 ps/div) voltage (50 mv/div) voltage (50 mv/div) voltage (50 mv/div) voltage (50 mv/div) ddj = 1 ps* ddj = 1.2 ps** ddj = 2 ps*** ddj = 2 ps*** *input signal ddj = 6.4 ps ***input signal ddj = 11 ps **input signal ddj = 7.2 ps ***input signal ddj = 13 ps
NB7L11M http://onsemi.com 7 figure 8. ac reference measurement clk clk q q t phl t plh v inpp = v ih (clk) ? v il (clk) v outpp = v oh (q) ? v ol (q) figure 9. typical termination for output driver using external termination resistor (refer to application notes and8020/d and and8173/d) NB7L11M receiver device q clk q clk v cc 50 50 v cc 50 50 z = 50 z = 50 figure 10. differential input driven single ? ended figure 11. differential inputs driven differentially figure 12. v th diagram figure 13. v cmr diagram clk v cc gnd v ih v ihmin v ihmax v thmax v th v th v thmin v cmmax v cmmax clk v cmr v cc gnd clk clk v th v th clk clk v ilmax v il v ilmin clk v ilclkmax v ihclkmax v (clk) = v ihclk ? v ilclk v ilclktyp v ihclktyp v ilclkmin v ihclkmin
NB7L11M http://onsemi.com 8 q q v cc 16 ma 50 50 figure 14. cml output structure v ee table 6. interfacing options interfacing options connections cml connect v tclk , v tclk to v cc lvds connect v tclk , v tclk together clk input ac ? coupled bias v tclk , v tclk inputs within (v cmr ) common mode range rsecl, lvpecl standard ecl termination techniques. see and8020/d. lvttl, lvcmos an external voltage should be applied to the unused complementary differential input. nominal voltage is 1.5 v for lvttl and v cc /2 for lvcmos inputs.
NB7L11M http://onsemi.com 9 application information all NB7L11M inputs can accept pecl, cml, lvttl, lvcmos and lvds signal levels. the limitations for differential input signal (lvds, pecl, or cml) are minimum input swing of 75 mv and the maximum input swing of 2500 mv. within these conditions, the input voltage can range from v cc to 1.2 v. examples interfaces are illustrated below in a 50 environment (z = 50 ). 50 v cc clk clk 50 NB7L11M v cc v tclk v ee v cc q 50 50 cml driver v ee figure 15. cml to cml interface z q z figure 16. pecl to cml receiver interface 50 z z v cc v cc pecl driver clk clk 50 NB7L11M v ee v bias v tclk v ee r t r t v ee v cc r t 5.0 v 290 3.3 v 150 2.5 v 80 recommended r t values 50 50 v tclk v cc v tclk v bias
NB7L11M http://onsemi.com 10 50 z v cc v cc lvttl/ lvcmos driver clk clk 50 NB7L11M v ee v tclk v cc v ref lvcmos v cc ? v ee 2 lvttl 1.5 v recommended v ref values v tclk v ref no connect* no connect 50 z v cc v cc lvds driver clk clk 50 NB7L11M v ee v tclk v ee v tclk z figure 17. lvds to cml receiver interface figure 18. lvcmos/lvttl to cml receiver interface *or 60 pf to gnd ordering information device package shipping ? NB7L11Mmn qfn ? 16 123 units/rail NB7L11Mmng qfn ? 16 (pb ? free) 123 units/rail NB7L11Mmnr2 qfn ? 16 3000 tape & reel NB7L11Mmnr2g qfn ? 16 (pb ? free) 3000 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB7L11M http://onsemi.com 11 package dimensions 16 pin qfn mn suffix case 485g ? 01 issue b 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 ??? ??? ??? 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x exposed pad notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k 0.20 ??? l 0.30 0.50 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 NB7L11M/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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